In efforts to achieve DC free recording of data signals, modulation codes of form M/N, where M , N are positive integers, have been employed in magnetic recording systems. The ratio M/N is normally referred to as the code rate. In order to obtain a small coding overhead, larger code rates have been sought after. However, the sizes of practical code rates are usually limited by the memory requirements and/or circuit complexity for encoding and decoding. The larger the value of M, the larger memory and/or circuit complexity is required.
One major drawback in constructing a helical scan magnetic tape recording/ reproducing apparatus is to generate DC free signals. DC free signals are necessary because the input and output signals have to be transferred to and from magnetic tape through a rotary transformer which is generally not responsive to DC signals. Several codes such as the 8/9, 8/10 and 9/10 codes have been proposed to overcome this bottleneck with considerable success. These codes are of form M/N where, 1) M is the number of input or decoded bits, 2) N is the number of output or encoded bits, and 3) both M and N are positive integers. Implementation of these codes usually requires memory elements such as ROMS, RAMS, or PROMS. This somewhat limits the practicality of these codes, especially for applications where light weight and low power recorders are usually indispensable. More specifically, in order to achieve low data overhead, one would expect the values of both M and N to be large. This imposes higher power consumption and larger packaging size. So one desirable feature to achieve is to obtain small memory or memoryless implementations of these codes.
A code is DC free when the digital sum variation (dsv) of any encoded sequence of digital data bits is bounded. The dsv of an encoded sequence may be simply defined as the difference between the number of ones and the number of zeros. When the number of ones is greater than the number of zeros, the dsv is positive (+); when the number of zeros is greater than the number of ones, the dsv is negative (-); and, when the number of ones and zeros are equal, the dsv is zero (0). For convenience, this term shall be used hereafter. The dsv of each codeword is usually called the codeword digital sum (or cds).
In general, an M/N modulation code is defined to be a code that provides one-to-one or one-to-more-than-one mapping of an M bit input sequence into an N bit output sequence. The usual convention calls each group of M input bits an input codeword and each group of N output bits an output codeword. Encoding is a process that provides such a mapping. Decoding is simply a process of accepting the encoded sequence and trying to recover the original input sequence. For convenience, there shall be used in this application the conventional notation (d,k,M,N,r) to signify a run-length limited modulation code where:
d=the minimum number of consecutive zeros between ones
k=the maximum number of consecutive zeros between ones
M=the number of decoded bits
N=the number of encoded bits
r =the number of distinct codeword lengths contained within the code.
In addition, the following parameters are defined as follows:
R=code rate=M/N
F=code frequency span=(k+1)/(d+1)
D=code density M*(d+1)/N
In general, in generating an M/N code where M=N-1 and M and N are positive integers, it is desirable to try to achieve the following:
1. To obtain as small a value k as possible and at the same time to obtain as large a value d as possible. This is to achieve a small frequency ratio k+1/d+1 and a large code density. (In case d=0, the code density is identical to the code rate).
2. To achieve a DC free encoded sequence, i.e., to have the dsv value bounded. The value should be bounded to a small value so that low frequency content is low. This is referred to as the dsv range.
3. To achieve a mapping from M to N such that dsv variance is small.
4. To obtain a mapping from M to N that would yield a high percent number of codewords with dsv=0. This is to try to maintain dsv value to zeros.
5. To try to generate an algorithm that would require small digital storage space, minimum circuit complexity, and low power consumption.